Alta Pattern Set			15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	
SKIP																			
CCD:	E2V  D09F		#NAME?																
System:	16 Bit		- step 0 must be final resting  state																
Pattern	M16HS1C																		
Date:	6/1/2009	Time (nS)	FIFO WR	SAM 2	SAM 1	CLAMP 16	CLAMP 12	CON 16	CON 12	INT 2	INT 1	RESET 2	RESET 1	S3	S2	S1	R	Stop	Row
	Mask		0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	0	
	REFERENCE	0	0	0	0	0	0	0	0	0	0	1	1	0	1	1	0	0	1
		20	0	0	0	0	0	0	0	0	0	1	1	0	1	0	1	0	2
		40	0	0	0	0	0	0	0	0	0	1	1	0	1	0	1	0	3
		60	0	0	0	0	0	0	0	0	0	1	1	0	1	0	1	0	4
		80	0	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	5
		100	0	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	6
		120	0	0	0	0	0	0	1	0	0	1	1	1	0	0	0	0	7
		140	0	0	0	1	0	0	1	0	0	1	1	1	0	0	0	0	7
		160	0	0	0	1	0	0	1	0	0	1	1	1	0	0	0	0	8
		180	0	0	0	0	0	0	1	0	1	1	1	1	0	0	0	0	9
		200	0	0	0	0	0	0	1	0	1	1	0	1	0	0	0	0	10
	 	220	0	0	0	0	0	0	1	0	1	1	0	1	0	0	0	0	31
	 	240	0	0	0	0	0	0	1	0	1	1	0	1	0	0	0	0	32
	 	260	0	0	0	0	0	0	1	0	1	1	0	1	0	0	0	0	33
		280	0	0	0	0	0	0	1	0	1	1	0	1	0	0	0	0	34
		300	0	0	0	0	0	0	1	0	1	1	0	1	0	0	0	0	35
	END	320	0	0	0	0	0	0	1	0	1	1	0	1	0	0	0	0	36
	BIN 1	340	0	0	0	0	0	0	1	0	0	1	0	1	0	0	0	0	37
	END	360	0	0	0	0	0	0	1	0	0	1	0	1	0	0	0	0	38
	SIGNAL	380	0	0	0	0	0	0	0	0	0	1	0	0	0	1	0	0	39
		400	0	0	0	0	0	0	0	0	0	1	0	0	0	1	0	0	40
		420	0	0	0	0	0	0	0	1	0	1	0	0	0	1	0	0	41
		440	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	42
		460	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	61
		480	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	62
		500	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	65
		520	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	66
		540	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	67
		560	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	68
		580	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	69
		600	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	70
		620	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	71
	END	640	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	72